The present invention relates to semiconductor device fabrication and, more specifically, to drain extended metal-oxide-semiconductor (DEMOS) transistors, design structures for DEMOS transistors, and methods of fabricating DEMOS transistors.
DEMOS transistors are high-voltage devices that differ both functionally and structurally from low-voltage devices. DEMOS transistors are utilized in an integrated circuit to switch voltages on a chip that are higher than typical logic voltages. DEMOS transistors feature a depleted drift region in series with a transistor drain so that a portion of the switched voltage is dropped across the drift region to protect the transistor gate dielectric. This structural modification reduces the electric field at the drain-side edge of the gate dielectric and thereby permits a DEMOS transistor to reliably switch comparatively high voltages without resorting to a thickened gate dielectric to avoid breakdown.
DEMOS transistors also present a high output impedance, which makes DEMOS transistors attractive for switching comparatively high voltages at input/output (I/O) terminals or pins in high frequency applications, such as RF-CMOS chip designs. Unfortunately, DEMOS transistors lack robustness when exposed to electrostatic discharge (ESD) events.
Improved device structures, fabrication methods, and design structures are needed for the ESD protection devices used to protect DEMOS transistors from damage during an ESD event.